1. Field of the Invention
The present invention relates to a mesh clock distribution circuit and a test method of the same.
2. Description of the Related Art
As IT (Information Technology) has rapidly progressed, transmission rate at which data is transmitted through transmission lines is increasingly enhanced. Therefore, functionality of processing on a large scale in a high speed is required for electronic circuits installed in devices connected to transmission lines. In design of an electronic circuit for implementing the functionality, distribution of a high speed clock having a small skew to many flip-flops (FF) may allow the design to be easy.
As one of clock distribution structures for the purpose, a mesh structure is conventionally used in which outputs of buffers in a relay stage or a final stage are short-circuited to reduce a skew, distributing a clock to flip-flops (FF).
FIG. 4 is a view illustrating a configuration of a clock distribution circuit disclosed in Japanese Patent Laid-Open No. 2003-92352 (FIG. 1). A clock signal is input to clock buffers 105 for driving mesh wiring through a clock buffer tree 107, and an output of each clock buffer 105 is supplied to each of cross points of a clock mesh 104 disposed on a chip.
The clock buffer tree 107 distributes the clock signal so that an input clock signal to each clock buffer 105 for the mesh wiring all has a uniform delay. An input terminal of each buffer 109 in a final stage for supplying a clock, is connected to a wiring part between the cross points of a clock mesh 104, and an output of each buffer 109 in the final stage is input, as the clock signal, to a flip-flop (FF) 108 disposed in the chip, whereby the skew is reduced.